The present invention relates to a bidirectional bus-repeater controller, and more particularly to a bidirectional bus-repeater controller for controlling a bidirectional repeater placed in a bidirectional busline in a semiconductor device such as VLSI, and further particularly to a bidirectional bus-repeater controller for controlling bidirectional signal transmissions in the bidirectional repeater wherein a relatively long bidirectional busline is divided.
As the semiconductor device such as VLSI has multi-functions, complicated operations of controlling the bidirectional bus-repeater on the bidirectional bus-repeater is required, for which reason the bus line is made unidirectional or signal lines are used as dedicated lines. Upon progresses of the system-on-chip, it is required to reduce the delay in signal transmission on a wiring region or a wiring.
In order to respond to the above requirement, it was proposed to use the bidirectional bus. It was further proposed to use the repeater for suppressing the signal delay due to the long interconnection or wiring, which is disclosed in Addison-Wesley Publishing Company 1990, xe2x80x9ccircuits interconnections and packaging for VLSIxe2x80x9d. It was further proposed to place the bidirectional bus repeater on the bidirectional bus, which is disclosed in Japanese laid-open patent publication No. 6-28304.
FIG. 1 is a block diagram illustrative of a conventional bidirectional bus-repeater controller. The conventional bidirectional bus-repeater controller has the following circuit configuration. A first set of a first bus driver 121 and a first bus receiver 131 is connected to a bus line 101. The first set of the first bus driver 121 and the first bus receiver 131 operates the signal transmission and receiving with the bus line 101 upon input of a first bus driver control signal S141. A second set of a second bus driver 122 and a second bus receiver 132 is connected to the bus line 101. The second set of the second bus driver 122 and the second bus receiver 132 operates the signal transmission and receiving with the bus line 101 upon input of a second bus driver control signal S142. A third set of a third bus driver 123 and a third bus receiver 133 is connected to the bus line 101. The third set of the third bus driver 123 and the third bus receiver 133 operates the signal transmission and receiving with the bus line 101 upon input of a third bus driver control signal S143.
First and second bidirectional repeaters 102 and 103 are connected on the bus line 101. The first and second bidirectional repeaters 102 and 103 arc connected to a controller 108 which is further connected to an internal buffer which is not illustrated. The first bidirectional repeater 102 receives bidirectional repeater control signals 161L and 161R, so that the first bidirectional repeater 102 operates bidirectional transmissions of data signals and address signals on the bus line 101. The second bidirectional repeater 103 receives bidirectional repeater control signals 162L and 162R, so that the second bidirectional repeater 103 operates bidirectional transmissions of data signals and address signals on the bus line 101.
The single controller 108 controls the plural bidirectional repeaters 102 and 103. It is necessary that a large number of control signal lines L are provided for transmissions of the bidirectional repeater control signals 161L, 161R, 162L and 162R from the controller 108 to buffers in the directional repeaters 102 and 103.
As the VLSI is required to scale down the internal structure, the number of processing circuit blocks connected to the bus line 101 is increased whereby the number of the bidirectional repeaters is increased, whereby a large number of the control signal lines L is required. As a result, layout f the control signal lines and also layout of other signal lines are so made that the control signal lines and the other signal lines are made long, whereby signal delays are likely to appear on the control signal lines and the other signal lines.
The conventional bidirectional bus-repeater controller is disadvantageous in that layout of the control signal lines is made large whereby signal delays appear. This makes it difficult to improve high speed performance of the data processing.
In the above circumstances, it had been required to develop a novel bidirectional bus-repeater controller free from the above problem.
Accordingly, it is an object of the present invention to provide a novel bidirectional bus-repeater controller free from the above problems.
It is a further object of the present invention to provide a novel bidirectional bus-repeater controller wherein a relatively long bus line is divided so that bidirectional signal transmissions are controlled by the individual bidirectional repeaters to suppress signal delays and to allow improvement in high speed performance of data processings.
The present invention provides a bidirectional bus repeater controller comprising: a bidirectional bus line for bidirectional transmissions of signals; at least a bidirectional repeater on the bidirectional bus line for controlling bidirectional transmissions of signals on the bidirectional bus line; at least a bus driver connected to the bidirectional bus line for transmitting inputted signals to the bidirectional bus line in accordance with a bus driver control signal; at least a bus receiver connected to the bidirectional bus line for receiving signals from the bidirectional bus line; and a logic circuit extending along the bidirectional bus line and being connected to the at least bidirectional repeater for transmitting bidirectional bus repeater control signals to the at least bidirectional repeater upon input of the bus driver control signal.
The above and other objects, features and advantages of the present invention will be apparent from the following descriptions.